1. Field of the Invention
The present invention generally relates to a phase detector, and more particularly to a phase detector for a clock and data recovery architecture.
2. Description of Related Art
A clock and data recovery (CDR) circuit plays an important role in high speed Serializer/Deserializer (SERDES) design. The clock and data recovery circuit is important for modern transceiver systems to reduce jitter and improve signal quality. Phase-locked-loop (PLL)-based CDR is widely employed in monolithic implementations of continuous-mode CDR circuits. Traditionally, the CDR utilizes a phase detector to perform phase locking.
The common phase detectors for the CDR are mainly linear phase detector and bang-bang phase detector. FIGS. 1A and 1B illustrate the characteristic curves of the linear phase detector and the bang-bang phase detector, respectively. As shown, the current is charged/discharged linearly with the phase error in the linear phase detector, which has smaller output jitter. However, the narrow pulse, due to the small phase error, may not work well at high data rate. On the contrary, the bang-bang phase detector is suitable for operating in high speed circuit, but its generated jitter is too large.
Therefore, a need has arisen to propose a novel phase detector which can reduce the jitter when locking phase, and also can be suitable for operating in high speed circuit.